1. Field of the Invention
This invention relates to a controllable delay clock buffer and, more particularly, to a controllable delay clock buffer that provides spread spectrum modulation of the clock signal and zero cycle slip.
2. Description of Related Art
A controllable delay buffer is a device that accepts an input signal (typically a periodic clock signal) and provides an output that has its transition edges phase aligned (controlled) with respect to those of the input signal. The definition of a transition edge is a change in voltage or current from one stable state to another. Phase alignment implies that the measured phase (time) difference between the 2 edges of the input and output is less than a certain specified value.
Controllable delay clock buffers are typically connected to synchronize and buffer multiple identical output clock signals to an input reference clock. There is a minimum time delay between the output clock edges and the reference input clock edges, which relates to the phase alignment of the signals.
In the prior art, there are generally two types of controllable delay clock buffers. Conventional controllable delay buffers have both input and output clocks without spread spectrum modulation, but these devices provide no benefit in EMI reduction. On the other hand, spread spectrum-capable controllable delay buffers have an input reference clock that is spread spectrum modulated, passing the SS modulation undistorted to all output parallel clocks. There is a minimum delay between input and outputs, and the SS modulation is always maintained ON at all outputs.